1/8 tda7535 december 2003 n 20-bit resolution single ended output n analog reconstruction third order chebyshev filter n i 2 s input data format n on chip pll n system clock: 64 fs n 2 output channels n 0.9 vrms single ended output dynamic n 3.3v power supply n reset n sampling rate 36khz to 48khz description the tda7535 is a stereo, digital-to-analog converter designed for audio application, including digital inter- polation filter, a third order multibit delta-sigma dac, a third order chebyshev's reconstruction filter and a differential to single ended output converter. this de- vice is fabricated in highly advanced cmos, where high speed precision analog circuits are combined with high density logic circuits. the tda7535, ac- cording to standard audio converters, can accept any i 2 s data format. the tda7535 is available in so-14 package. the to- tal power consumption is less than 75mw. tda7535 is suitable for a wide variety of applications where high performance are required. its low cost and single 3.3v power supply make it ideal for sever- al applications, such as cd players, mpeg audio, midi applications, cd-rom drives, cd-interactive, digital radio applications and so on. an evaluation board is available to perform measurement and to make listening tests. so-14 ordering number: tda7535 delta/sigma cascade 20 bit stereo dac block diagram fir1 fir2 alu s&h i 2 s i 2 s pll clkout digital input 20 fir3 20 4 sd modulator thermo decoder & randomizer 3rd chebyshev sc filter diff to single converter analog output f s 8f s 23 64f s d02au1417
tda7535 2/8 absolute maximum ratings warning: operation at or beyond these limit may result in permanent damage to the device. normal operation is not guaranteed at these extremes. thermal data note: 1. in still air pin connections (top view) pin function symbol parameter value unit v dd v cc power supplies digital analog -0.5 to +4.6 -0.5 to +4.6 v v v aio analog input and output voltage -0.5 to (v cc +0.5) v v dio digital input and output voltage -0.5 to (v dd +0.5) v v di5 digital input voltage (5v tolerant) -0.5 to 6.5 v t j operating junction temperature range -40 to 125 c t stg storage temperature -55 to 150 c symbol parameter value unit r th j-amb thermal resistance junction to ambient (1) 85 c/w pin number pin name input/output power description 1 n.c. - - 2 sdata i i2s digital data input 3 sck i i2s clock input 4 n.c. - - 5 gnd_dig p digital ground 6 gnd_ana p analog ground 7 outsr o right channel single ended output 8 outsl o left channel single ended output 9 vcm p reference 1.65v externally filtered 10 vdd_ana p analog 3.3v-supply 11 n.c. - - 12 vdd_dig p digital 3.3v-supply 13 fsync i i2s left-right channel selector 14 resetn i reset (active low) n.c. sdata sck n.c. gnd_dig outsr gnd_ana outsl vdd_ana vcm n.c. vdd_dig fsync resetn 1 3 2 4 5 6 7 12 11 10 9 8 13 14 d01au1276a
3/8 tda7535 recommended dc operating conditions power consumption general interface electrical characteristics note: 1. the leakage currents are generally very small, <1na. the value given here, 1ma, is the maximum that can occur after an e lectro- static stress on the pin. 2. human body model. low voltage cmos interface dc electrical characteristics symbol parameter test condition min. typ. max. unit v dd 3.3v digital power supply voltage 3.15 3.3 3.45 v v cc 3.3v analog power supply voltage 3.15 3.3 3.45 v symbol parameter test condition min. typ. max. unit i dd total maximum current power supply @ 3.3v and t j = 125c 21.5 25 ma symbol parameter test condition min. typ. max. unit l il low level input current without pullup device v i = 0v (note 1) 1 m a l ih high level input current without pullup device v i = v dd (note 1) 1 m a i latchup i/o latch-up current v < 0v, v > v dd 200 ma v esd electrostatic protection leakage , 1 m a (note 2) 2000 v symbol parameter test condition min. typ. max. unit v il low level input voltage 0.2*v dd v v ih high level input voltage 0.8*v dd v v hyst schmitt trigger hysteresis 0.8 v dac electrical characteristics vdd = 3.3v; tamb = 25c; input signal frequency = sinus wave generated by audio precision sys.2; input signal amplitude = see notes; noise integration bandwidth = 20hz to 22khz (a- weighted) parameter test condition min. typ. max. unit noise + distortion (see note 1) @0db @-6dbb @-40db @-60db 89 94 96 96 db db db db total harmonic distortion see note 2 94 db dynamic range see note 3 96 db crosstalk see note 4 -95 db full scale output voltage v dd = 3.15 to 3.45v full scale input 0.8 0.9 1.0 vrms input sampling rate 36 48 khz
tda7535 4/8 note1: it is the ratio between the maximum input signal and the integration of the in-band noise after deducing the power of sig nal funda- mental. it depends on the input signal amplitude. in this case 0db means full scale digital, 1khz frequency used. note 2: it is the ratio of the rms value of the signal fundamental component at 0db (full scale digital) to the rms value of all of the harmonic components in the band. note 3: measured using the snr at -60db input signal, with 60db added to compensate for small input signal. note 4: left channel on with 0db/1khz input signal, right channel on with dc input signal. figure 1. i 2 s interface diagram passband ripple 0.12 db stopband @ 3db @ 90db 44.1khz sampling rate 21.53 24.80 khz interchannel gain mismatch 0.05 0.1 db dac electrical characteristics (continued) vdd = 3.3v; tamb = 25c; input signal frequency = sinus wave generated by audio precision sys.2; input signal amplitude = see notes; noise integration bandwidth = 20hz to 22khz (a- weighted) parameter test condition min. typ. max. unit fsync sdata sck 32 * sck 32 * sck 20 bits msb lsb 20 bits msb lsb left right
5/8 tda7535 figure 2. i 2 s timings (1) sck clock defines the fs, being the sample rate. this input clock needs a jitter below ~212ps rms (2) fsync switches inside the time window as specified w.r.t. to falling edge of sck figure 3. power up & reset sequence i 2 s bit clock (sck) must be present 20ms before reset release to allow pll locking. timing description minimum maximum unit t sck clock cycle (1) 1/(64*fs) - 150ps rms 1/(64*fs) + 150ps rms ns t sckpl sck phase low 0.5*t sck - 1% 0.5*t sck +1% ns t sckph sck phase high 0.5*t sck - 1% 0.5*t sck +1% ns t lrw- fsync switching time window before sck falling edge (2) 0 0.125*t sck -10 ns t lrw+ fsync switching time window after sck falling edge (2) 0 0.125*t sck -10 ns t sds sdata setup time 60 ns t sdh sdata hold time 30 ns t sckr sck rise time 1.5 ns t sckf sck fall time 1.5 ns t sck t sckpl t sds t lrw- t sckph t lrw+ t sdh valid fsync sdata sck valid t sckf t sckr t res t res min 50ms v dd reset d02au1418
tda7535 6/8 figure 4. frequency response figure 5. 10 m h bead inductor sdata 7 tp1 tp7 j4 bnc j3 bnc tp8 2 outsr sck tp2 3 fsync i 2 s tp3 13 gnd_dig 5 gnd_ana vcm 6 9 8 tp5 +3.3vana +3.3 vdig m p r2 10k 100nf(*) 100nf(*) c15 47 m f 10v (*) c7 10 m f 10v 10 m f 10 m f sw1 c16 100nf (*) tp6 outsl 10 vdd_ana 12 vdd_dig resetn outsr outsl 14 d02au1419b u4 (*) as close as possible to the pin
7/8 tda7535 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.30 0.004 0.012 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.01 d (1) 8.55 8.75 0.337 0.344 e 3.80 4.0 0.150 0.157 e 1.27 0.050 h 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) d dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so14 0016019 d
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